Key Responsibilities

• Define and drive the long-term strategy, vision, and roadmap for Select IO, clocking, and  SelectIO IP protocols technologies.
• Influence fabric architecture and integration strategies to optimize performance and scalability across AMD-AECG platforms.
• Develop and deliver technical content including webinars, white papers, reference designs, and conference demos.
• Engage directly with customers to understand challenges, gather insights, and champion their success.
• Collaborate across vertical and horizontal teams, including HW/SW Engineering and Architecture, to drive innovation in IP, software, and platforms.
• Shape Vivado design and debug tool strategies to accelerate time-to-market for Select IO and protocol designers.

Preferred Experience

• Proven experience in Product Management, Architecture, or Applications Engineering for Select IO, clocking, and high-speed protocols.
• Deep technical knowledge of SelectIO, clocking architectures, PCB design, and standards such as 1000Base-X, SGMII, RGMII, GMII, MIPI, ADC/DAC.
• Hands-on experience with FPGA-based Select IO and IP development, including fabric integration, emulation, and prototyping.
• Strategic leadership in roadmap definition and technology decision-making.
• Strong relationship-building skills with internal teams and external IP partners.
• Ability to translate complex technical concepts into actionable strategies and compelling narratives.

Education

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.